<span style='color:red'>Xilinx</span> Buys China AI Startup
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Xilinx Buys China AI Startup

Xilinx purchased DeePhi, a 200-person startup in Beijing, in a deal that shows the speed and global scale of the super-hot AI market. Analysts said that the move was likely an effort to grab hard-to-find deep-learning talent already developing neural-networking software for Xilinx FPGAs.The deal is not alone in showing how a fast-moving industry is outpacing government concerns about the ownership of technologies such as AI that both China and the U.S. have identified as critical.Founded by a group from Tsinghua and Stanford Universities, DeePhi has expertise in “deep compression, pruning, and system-level optimization for neural networks,” according to a press statement from Xilinx, one of the company’s Series A investors, in early 2017.DeePhi’s website claims that the company, founded in 2016, already has developed two hardware architectures. Its Aristotle runs convolutional neural nets for video and imaging recognition while its Descartes supports recurrent and other neural nets for speech recognition and runs on Xilinx FPGAs.The company is rumored to be the source of deep-learning acceleration in Samsung’s Exynos 9810 in the Galaxy S9 smartphone. Samsung is one of 10 backers that invested a total of more than $40 million in DeePhi last year. Other investors include Mediatek and seven mainly China-based venture capital groups.Although still early in its life, the startup was said to be seeking an exit amid many acquisition offers. “In today’s market, it is very hard to hire good machine-learning talent, so often the best alternative is to buy startups,” said Kevin Krewell, an analyst with Tirias Research.“This is an excellent move by Xilinx,” said Chris Rowen, a serial entrepreneur who met recently with DeePhi CEO Song Yao, who finished his undergrad degree at Tsinghua in 2015. “DeePhi has one of the best embedded neural-network teams in the industry — not just in China. This should help Xilinx solidify a spot at the grown-ups’ table for AI.”Another DeePhi co-founder was cited as a young innovator and recently spoke in a panel at DAC.Among its areas of expertise, Rowen cited the startup’s “real mastery of the concept of model compression in which trained models are transformed to smaller, denser models without loss of accuracy. They have widely accessible tools and hundreds, if not thousands, of users mapping networks through those tools.” He noted that the techniques improve computer throughput and energy efficiency and reduce memory requirements.Xilinx’s chief rival got an early lead in AI. The former Altera, now part of Intel, was tapped by Microsoft for a research program on data center accelerators that now has the web giant putting an FPGA on every new server that it buys and expanding its range of FPGA-based services.Xilinx declined to release financial terms of the acquisition but indicated that it aims to continue investing in the Beijing group.“Talent and innovation are core to realizing our vision,” said Salil Raje, executive vice president of Xilinx’s software and IP products group, in the company’s press statement. “Xilinx will continue to invest in DeePhi to advance our shared goal of deploying accelerated machine-learning applications in the cloud as well as at the edge.”
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Release time：2018-07-19 00:00 reading：3164 Continue reading>>
New <span style='color:red'>Xilinx</span> CEO Touts 'Adaptive Computing'
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New Xilinx CEO Touts 'Adaptive Computing'

　　Less than two months after taking the reigns at Xilinx, Victor Peng outlined a new strategy for the programmable logic stalwart that emphasizes technology for the data center and "adaptive computing," centered around what the company calls a new class of devices.　　Claiming performance advantages over high-end CPUs and GPUs for applications related to Big Data and artificial intelligence, Xilinx will begin rolling out a new type of multicore chip next year that emphasize compute capability and with both software- and hardware-level programmability.　　Xilinx — long the market leader in programmable logic devices — claims its adaptive compute acceleration platform (ACAP) goes far beyond the capabilities of FPGAs to deliver levels of performance and performance-per-watt unmatched by CPUs or GPUs. An ACAP consists of an FPGA fabric with distributed memory and hardware-programmable DSP blocks, a multicore SoC and one or more software-programmable compute engines, all connected through an on-chip network.　　The first family of ACAP devices, codenamed project Everest, will be implemented at the 7nm node by TSMC. Initial tapeouts of Everest devices are expected to tapeout later this year, with initial customer shipments expected in 2019. Key customers have already received Xilinx development tools for Everest ACAP devices, the company said.　　In an interview with EE Times, Victor Peng, Xilinx president and CEO, described the launch of ACAP devices as part of his broader strategy to move Xilinx "beyond FPGAs and supporting only hardware developers."　　Peng said ACAP devices are aimed at a broad set of applications in Big Data and AI, including video transcoding, database, data compression, search, AI inference, genomics, machine vision, computational storage and network acceleration.　　The introduction of ACAP marks by far the most clear-cut attempt by Peng to put his stamp on the company he assumed the helm of in January, succeeding Moshe Gavrielov as CEO. Peng told EE Times he would emphasize data center as an end market more than his predecessor, both because it is seen as a significant growth area and also because it can benefit from what he said is "an orders of magnitude" performance-per-watt advantage that Xilinx can offer versus competitors.　　In addition to a greater emphasis on data center, the strategy for Xilinx outlined by Peng includes shooting for accelerated growth in core markets such as automotive, wireless infrastructure, wired communications, broadcast, aerospace/defense, medical, test and measurement, consumer technologies, and others.　　"While FPGA and Zynq SoC technologies are still core to our business, Xilinx is not just an FPGA company anymore," Peng said.　　Peng also articulated a desire to market more directly to software developers, which he said can target ACAP-based systems using tools like C/C++, OpenCL and Python. Xilinx said an ACAP can also be programmable at the RTL level using FPGA tools.　　An ACAP is also characterized by highly integrated programmable I/O functionality, ranging from integrated hardware programmable memory controllers, advanced serdes technology and RF-ADC/DACs, to integrated High-Bandwidth Memory, depending on the specific device, according to Xilinx.　　ACAP products will ultimately encompass devices with more than 50 billion transistors, according to Peng. The launch is the result of four years of development by more than 1,500 with a total development price tag of more than $1 billion, he said.
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Release time：2018-03-20 00:00 reading：3325 Continue reading>>
Samsung, <span style='color:red'>Xilinx</span> Back Programmable Chip Startup
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Samsung, Xilinx Back Programmable Chip Startup

　　Programmable logic vendor Xilinx Inc. and the venture capital arm of Samsung Electronics were among a handful of firms to provide $9.5 million in funding to Efinix, a developer of silicon-based programmable product platforms based in Silicon Valley.　　Efinix (Santa Clara, Calif.), founded in 2012, has raised a total of $16 million. The company says its Quantum programmable technology delivers a four-fold power, performance and area advantage over traditional technologies. The technology is based on what Efinix calls an XLR (exchangeable logic and routing) cell that can function as either a look-up table (LUT)-based logic cell or  routing switch encoded with a scalable, flexible routing structure.　　According to Efinix, this technology improves the active area utilization by 4X compared with traditional FPGAs, resulting in up to 4X area efficiency and 2X power consumption advantage.　　According to the company's website, Efinix is currently developing silicon products based on Quantum and expects to begin sampling in Decemeber of this year.　　The funding round was led by Xilinx and Hong Kong X Technology Fund, an investment firm supported by Sequoia Capital China and focused on fast-growing tech firms. Samsung Ventures, Hong Kong Inno Capital and Brizan Investments also participated in the funding round, according to Efinix.　　Sammy Cheung, co-founder, CEO, and president of Efinix, said in a press statement that the company plans to use the funding to launch a number of joint development projects in the coming months in addition to the chips.　　"High-volume applications and markets are prime targets for our Quantum-accelerated products," Cheung said.　　Also in the press statement, Salil Raje, senior vice president of the software and IP products group at Xilinx, said, "Efinix’s solution can address a wide variety of applications that are typically not served by today’s FPGAs."　　An unnamed representative from Samsung Ventures said Samsung envisions many applications that feature Quantum technology embedded inside ASICs, ASSPs or FPGAs.
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Release time：2017-09-30 00:00 reading：3382 Continue reading>>
TMSC, ARM, <span style='color:red'>Xilinx</span>, Cadence Partner on 7-nm Process
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TMSC, ARM, Xilinx, Cadence Partner on 7-nm Process

　　Xilinx, ARM, Cadence, and TSMC have announced a partnership to build a test chip in 7-nm FinFET process technology for delivery next year that promises to speed data center applications.　　The chip will be the first demonstration in silicon of Cache Coherent Interconnect for Accelerators (CCIX) enabling multi-core high-performance ARM CPUs working via a coherent fabric with off-chip FPGA accelerators, said the partners in a press statement.　　Accelerating applications in data centers is a growing requirement due to power and space constraints. Applications such as big data analytics, search, machine learning, wireless 4G/5G, and network processing benefit from acceleration engines that move data effectively among various system components.　　CCIX will allow components to access and process data irrespective of where it resides without the need for complex programming environments. CCIX will use existing server interconnect infrastructure and deliver higher bandwidth, lower latency, and cache coherent access to shared memory.　　This will result in a significant improvement in the effectiveness of accelerators as well as overall performance and efficiency of data center platforms, lowering the barrier to entry into existing server systems and improving the total cost of ownership of acceleration systems.　　The test chip, implemented on TSMC’s 7-nm process, will be based on the latest ARM DynamIQ technology, CMN-600 coherent on-chip bus, and foundation IP.　　“With the surge in artificial intelligence and big data, we’re seeing increasing demand for more heterogeneous compute across more applications,” said Noel Hurley, vice president and general manager of ARM's Infrastructure Group. “The test chip will not only demonstrate how the latest ARM technology with coherent multichip accelerators can scale across the data center but reinforces our commitment to solving the challenge of accessing data quickly and easily.”　　To validate the complete subsystem, Cadence provided key I/O and memory subsystems, which include the CCIX IP solution (controller and PHY), PCI Express 4.0/3.0 (PCIe-4/3) IP solution (controller and PHY), DDR4 PHY, peripheral IPs such as I2C, SPI and QSPI, as well as associated IP drivers. Cadence verification and implementation tools are being used to build the test chip.　　The test chip provides connectivity to Xilinx’s 16-nm Virtex UltraScale+ FPGAs over CCIX chip-to-chip coherent interconnect protocol.　　“Our Virtex UltraScale+ HBM family is built using TSMC’s third-generation CoWoS technology, which is now the industry standard assembly for HBM integration and cache-coherent acceleration with CCIX," said Victor Peng, chief operating officer at Xilinx.　　The test chip will tape out early in the first quarter of 2018, with silicon availability expected in the second half of 2018.　　“By building an ecosystem for high-performance computing with our collaboration partners, we will enable our customers to quickly deploy innovative new architectures at 7 nm and other advanced nodes for these growing data center applications,” said Babu Mandava, senior vice president and general manager of the IP Group at Cadence. “The CCIX industry standard will help drive the next generation of interconnect that provides the high-performance cache coherency that the market is demanding.”　　Artificial intelligence and deep learning will significantly impact industries including media, consumer electronics, and healthcare, according to Cliff Hou, TSMC vice president, Research & Development/Design and Technology Platform.　　“TSMC’s most advanced 7-nm FinFET process technology provides high-performance and low-power benefits that satisfy distinct product requirements for High-Performance Computing applications targeting these markets,” said Hou.
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Release time：2017-09-12 00:00 reading：3154 Continue reading>>

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